1. Field of the Invention
The present invention generally relates to the art of electronic circuitry, and more specifically to a thresholdless differential comparator circuit for an Analog-to-Digital Converter (ADC) or other application.
2. Description of the Related Art
A conventional Analog-to-Digital Converter (ADC) generally comprises a bank of single-ended voltage comparators as illustrated in FIG. 1. The reference numeral 10 designates a 4-bit (16 discrete value) comparator circuit comprising a voltage divider 12 including a plurality of resistors 12.sub.0 to 12.sub.16 that are connected in series between a positive voltage supply V.sub.DD and ground. The voltages at the upper ends of the resistors 12.sub.0 to 12.sub.16 increase progressively from the bottom to the top of the voltage divider 12.
The circuit further comprises a plurality of single-ended voltage comparators 14.sub.0 to 14.sub.15 having inverting inputs connected to the upper ends of the resistors 12.sub.0 to 12.sub.15 respectively. An analog input voltage V.sub.in is applied to the non-inverting inputs of the comparators 14.sub.0 to 14.sub.15, which produce output voltages V.sub.o1 to V.sub.o15 at their single-ended outputs.
An N-bit ADC requires 2.sup.N resistors and 2.sup.N -1 comparators. Thus, the circuit 10 comprises, for a 4-bit converter, 16 resistors and 15 comparators. In operation, each comparator 14.sub.0 to 14.sub.15 produces a logically high output if the input voltage V.sub.in is higher than the voltage at its inverting input, and vice-versa.
The values of the resistors 12.sub.0 to 12.sub.16 are selected such that the voltages at the upper ends thereof constitute a series of equally stepped reference voltages corresponding to the increments into which the analog input signal V.sub.in is to be digitized. Thus, all of the comparators 14.sub.0 to 14.sub.15 whose reference voltages are higher than the input voltage V.sub.in will produce low outputs, whereas all of the comparators whose reference voltages are lower than the input voltage V.sub.in will produce high outputs.
Although not explicitly illustrated, the circuit 10 further comprises a multiplexer or encoder that is responsive to the transition point from low to high output voltage from the comparators 14.sub.0 to 14.sub.15, and encodes the transition point to produce a digital value.
A major drawback of the conventional comparator 10 is that each of the comparators 14.sub.0 to 14.sub.15 operates at a different common mode voltage, which in the case of the circuit 10 of FIG. 1 is defined to be a voltage that is halfway between the voltages at the inverting and non-inverting inputs of the comparators 14.sub.0 to 14.sub.15.
Assuming, for example, that the input voltage V.sub.in can have a 2 V range from 1 V to 3 V, the reference voltage applied to inverting input of the lowest comparator 14.sub.0 will be approximately 1 V whereas the reference voltage applied to the highest comparator 14.sub.15 will be 3 V. If the input voltage V.sub.in has an average value of 2 V, the common mode voltage of the comparator 14.sub.0 is 2 V-1 V=1 V, whereas the common mode voltage of the comparator 14.sub.15 is 3 V-1 V=2 V.
In general, depending on the value of the input signal V.sub.in, the common mode voltage of the comparators 14.sub.0 to 14.sub.15 can range from 0 V to 3 V, the entire range of the input signal V.sub.in. Thus, the comparators 14.sub.0 to 14.sub.15 must be designed with sufficient dynamic range to accommodate this magnitude of input signal variation.
Each of the reference voltages can be considered as a "threshold" voltage for the particular comparator to which it is connected and is different for each comparator in the bank. Since a practical comparator is implemented as a differential amplifier (emitter-coupled in a bipolar transistor circuit or source-coupled in a field-effect transistor circuit), the input common-mode voltage can have a strong effect on the input-output transfer and delay characteristics.
These common-mode induced differences can cause an effective decrease in the overall resolution of the comparator bank. In addition, high frequency white noise due to crosstalk can become superimposed onto the input line resulting in further limits on the achievable resolution.